Semiconductor technology has been following a constant trend of reducing the dimensions of integrated components, such as metal lines, resistors, diodes, transistors, etc. The reduction in dimensions allows more devices within a single integrated circuit, thereby providing more advanced functionality to the user. However, the minimum dimensions of modern semiconductor technology are such that it is becoming increasingly difficult not only to further reduce them, but also to precisely control them.
In particular, in the field of finfet transistors, when processing transistors with fin width below, for instance, 20 nanometers, it is technologically rather complex to get a single exact value for the fin width within an entire wafer, or even within a single chip. In particular, for technologies using such small dimensions, the width of the fin is defined by double patterning and this technology results in a range of values for the fin width over the wafer. Here, by “finfet,” it is intended finfets with perpendicular side walls, or with tilted side walls, or double-gate finfet.
The threshold voltage VT of the finfet is, however, dependent on the width of the finfet. The off-current of the transistor is as well dependent on the threshold voltage VT. Therefore, if the fin width is not a single common value over the entire wafer, but rather a range of values, the off-current will change significantly, from transistor to transistor, as the fin width varies, thereby creating a spread of off-current values.